Integrated circuits may contain tens or even hundreds of embedded memories in conjunction with other circuitry. During the manufacturing process, one or more of such memories will exhibit failures that may adversely impact the ability of the integrated circuit housing them to operate in its intended manner.
In order to increase yields of such integrated circuits, a large plurality of which may be found on a single integrated circuit wafer, a number memory repair techniques have been developed.
Typically such techniques involve designing within each memory circuit, a plurality of redundant memory circuits, whether in the form of additional columns, rows or locations, which can be dynamically substituted for locations within the memory which have been a priori diagnosed (during a testing phase of the integrated circuit manufacturing process) as exhibiting failure characteristics.
Then, when the integrated circuit is installed and powered up, information is conveyed to the memory, at the time of start up, instructing it to access a location within the redundant memory whenever a failed memory location is actually sought to be accessed. In this fashion, so long as a properly functioning redundant memory location may be accessed as a proxy for any failed memory locations within the memory, the memory may be said to be repaired and available for use within the integrated circuit, with the consequence that in the absence of other non-reparable errors within the integrated circuit, the integrated circuit will operate in its intended fashion.
Initial attempts at memory repair were made on an individual memory basis, as shown in prior art FIG. 1. The memory 100 comprises both conventionally addressable locations (not shown) as well as at least one bank of redundant memory locations (not shown), which may be configured as one or more columns or rows commensurate in dimension with a corresponding column or row of the addressable locations, or as one or more discrete memory locations.
In addition to conventional bus signals (not shown), including address and data lines, memory 100 comprises repair inputs comprising at least one repair address bus 110 and a repair enable control line 111 corresponding thereto. The repair address bus 110 has a number of signal lines corresponding to the number of bits used to address the bank of redundant memory locations, whether configured as a column, row or as a discrete memory location or word. For example, it is common to replace all columns associated with a memory data input/output port if any of the columns is defective. In such case, the repair address bus 110 may be configured simply to designate the number associated with the particular memory data input/output port in issue.
In some implementations, the repair address bus 110 and the repair enable control line 111 may be encoded in a common signal for convenience.
In order to repair one or more conventionally addressable locations of the memory 100, the corresponding address of the addressable memory segment or location, for which the redundant bank of memory locations is to be substituted, is presented at the repair address bus 110 and the repair enable control line 111 is configured to indicate that a repair is to be effected. The addressable location data is preferably stored in a non-volatile memory or register but in any event serves to alert an associated memory controller to access the corresponding redundant data location or segment when and if access to a location addressed by the addressable location data is attempted.
While preferably, the repair address bus 110 is otherwise held at an initialized value, such as all 0s, typically, memory repair systems such as the one described will ignore any value presented at the repair address bus 110 unless the repair enable control line 111 indicates that a repair should be effected.
In a memory repair system, there may only be one redundant location or segment available for use, in which presenting the address of the addressable location or segment to be repaired at the repair address bus 110 may be sufficient. Those having ordinary skill in this art will appreciate that where a plurality of such redundant locations and/or segments are available, the repair address bus 110 may contain a plurality of pairs of repair address and repair enable inputs. Alternatively, in addition to data lines to present the address of the addressable memory location or segment to be repaired, the repair address bus 110 may comprise a plurality of address lines to access one of a plurality of registers or memories in which the data, consisting of the address information and the corresponding repair enable input, may be stored, corresponding to one of a plurality of redundant locations or segments.
Such parallel repair interfaces, in which the repair information is applied directly to the memory input, are suitable where repair information is local to the particular memory being serviced.
However, there have been a number of attempts at developing a centralized memory repair system, in part because generally only a small subset of a memory and only a small number of memories (on the order of 10) located on an integrated circuit will fail. Centralizing the repair information may permit considerable compression, on the order of 10 to 1 or even more, of the silicon resources dedicated to repair functions.
Typically, and for the purposes of the present discussion, the centralized location is denoted a fuse box and the individual repair information data contained therein are denoted as fuses. Historically, this comes from the name of some of the common types of non-volatile memory used to implement the fuse box, namely laser fuse or e-fuse memory. Those having ordinary skill in this art will appreciate that other types of non-volatile memory, including but not limited to flash memory may also be appropriate to implement the fuse box.
In conjunction therewith, it has been found that a serial repair interface, such as is shown in prior art FIG. 2, may be more practical, inasmuch as a serial transfer approach minimizes the integrated circuit real estate that may be otherwise dedicated to distribution of repair information.
Additionally, the serial transfer approach permits a uniform interface for repair inputs, irrespective of the length (and concomitant number of data lines) of the address bus for addressing locations for repair or the number of redundant segments or locations housed thereon. As may be appreciated, the particular configuration of both addressable and redundant memory within a given memory circuit will impact on the number of address and data lines to be presented to it as repair inputs.
Furthermore, circuit design methodologies have tended to favour the use of pre-designed circuit blocks for modular insertion into integrated circuit designs. Implementing centralized repair strategies on circuits making use of such pre-designed circuit blocks is facilitated by the uniform interface provided by such serial transfer approaches.
In memories having serial repair inputs, such as memory 200, an internal register (in addition to such register or memory for storing the address(es) of the addressable location(s)) or Built-In Self-Repair (BISR) register 220, which may be a shift register, may be provided on chip. Such BISR 220 may accept as inputs a serial input line 221, a repair reset line 222 and a repair clock signal 223, and generate a serial output line 224. The serial input line 221 transmits both data on addressable location(s) for repair and a repair enable signal corresponding thereto from the centralized fuse box. This serial data is clocked into the memory 200 and into the BISR 220 by the repair clock signal 223, which is centrally generated. The repair reset signal 222 may be used to initialize the BISR 220 prior to clocking in repair data.
Once the repair data comprising an addressable location and enable pair is received by the BISR 220, this information may be presented and preferably stored in a register or memory location to the memory controller to effect the repair as discussed above along a repair address bus 210 and a repair enable control line 211 comparable to their counterparts shown in FIG. 1.
Preferably, the BISR 220 presents its contents as a serially clocked output along serial output line 224. This permits the functionality of the BISR 220 to be tested and/or monitored. Additionally, this permits the establishment of a “daisy-chain” of serial lines from successive memories on the integrated circuit so that a single set of serial data and clocking lines may emanate from the fuse box for the purpose of effecting memory repairs.
The art is replete with examples of centralized fuse box approaches to memory repair systems. An early example is disclosed in U.S. Pat. Nos. 6,363,020 and 6,556,490, respectively entitled “Architecture with multi-instance redundancy implementation” and “System and method for redundancy implementation in a semiconductor device” and issued Mar. 26, 2002 and Apr. 29, 2003 respectively to Shubat et al, which discloses a fuse box to provide fuses to each memory in a memory architecture having redundancy. A fuse box register is provided outside a memory macro and serves an arbitrary number of memories connected in a daisy chain. The fuse box register contains a plurality of fuses used for storing locations of defective rows and columns of a main memory array so that during power-up or after blowing the fuses, the fuse data is transferred to a plurality of volatile redundancy scan flip-flops, connected in a scan chain, both in the fuse box register as well as within the respective memories. This permits the fuse box register to be thereafter deactivated in order to eliminate quiescent current through the fuses, resulting in considerable power savings. During operation, the fuse contents are scanned into individual flip-flops organized as volatile scan registers of the memory instances. The redundant elements may be pre-tested in an override mode by bypassing the fuses and directly scanning arbitrary patterns into the redundancy scan flip-flops.
The Shubat et al systems do not perform any compression of the fuse data, but rather make use of memory-specific information, in which the number of fuses and redundancy flip-flops in the fuse box register and containing the fuse data exactly match the number and configuration of the redundancy flip-flops in the memory instances. Moreover, they are unable to support memories incorporating a mixture of parallel and serial repair approaches. Further, during testing of a plurality of integrated circuits on a single wafer to identify faults in the memories embedded therein, a considerable amount of information may be delivered to the tester in parallel causing a processing overload.
United States Patent Application No. 2007/0046343 entitled “Automation of fuse compression for an ASIC design system” filed by Adams et al and published Mar. 1, 2007 discloses a method and system for repairing defective memory in a semiconductor chip having memory locations, redundant memory and a central location for ordered fuses. The ordered fuses identify, in compressed format, defective sections of the memory locations for replacement by sections of the redundant memory. The ordered fuses have an associated fuse bit pattern which sequentially represents the defective sections in compressed format. The memory locations are wired together in order and a shift register of latches is provided through the memory locations corresponding to the identified order. Each of the latches is associated with a corresponding bit of an uncompressed bit pattern, comprising a sequence of bits representing the defective sections in uncompressed format, from which the fuse bit pattern is derived. While Adams et at provides an on-chip controller to reduce the amount of information presented to an off-chip tester during a testing phase and introduces a fuse data compression scheme, the disclosed system remains specific to the number, size and configuration of the embedded memory locations and incapable of supporting memories incorporating a mixture of parallel and serial repair approaches.
U.S. Pat. No. 6,898,143 entitled “Sharing fuse blocks between memories in hard-BISR” and issued “May 24, 2005” to Puri et al (“Puri1”) discloses a Built-In Self-Repair (BISR) scheme in which a plurality of memories are serially connected to a fuse controller. A plurality of fuse blocks corresponding thereto is also serially connected to the fuse controller. The number of fuse blocks is less than the number of memories and the fuse controller is configured so that memories may share the fuse blocks to reduce cost. Preferably, each fuse block includes fuse elements which can be programmed with an instance number of a memory for repair. The fuse block reduces routing congestion and is preferably configured to flexibly assign any fuse block to any memory for repair. The programmable fuse elements are preferably loaded into a counter forming part of the fuse controller, which ensures that correct block information is loaded into the corresponding memory instance. While Puri1 discloses a fuse data compression scheme, the disclosed system remains specific to the number, size and configuration of the embedded memory locations and incapable of supporting memories incorporating a mixture of parallel and serial repair approaches. Further, it provides no relief to an off-chip tester from information overload during a testing phase.
In United States Patent Application No. 2003/0196143 entitled “Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories” filed by Puri et al and published Oct. 16, 2003 (“Puri2”), there is disclosed a controller circuit configured to present one or more control signals to control one or more Built-In Self-Test (BIST) and Built-In Self-Repair (BISR) modes of operation. The disclosed BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution. The memory blocks may be remapped in response to the count values during one or more of the BISR operations. While Puri2 incorporates a central/shared fuse box concept, it does not disclose a fuse data compression scheme, the disclosed system remains specific to the number, size and configuration of the embedded memory locations and incapable of supporting memories incorporating a mixture of parallel and serial repair approaches and provides no relief to an off-chip tester from information overload during a testing phase.
In United States Patent Application No. 2005/0132255 entitled “Low-power SRAM E-fuse repair methodology” filed by Tran et al and published Jun. 16, 2005, a method is provided for substantially removing system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. While Tran et al use a shared fuse box architecture, they do not disclose a fuse data compression scheme, the disclosed system remains specific to the number, size and configuration of the embedded memory locations and incapable of supporting memories incorporating a mixture of parallel and serial repair approaches and provides no relief to an off-chip tester from information overload during a testing phase.
In United States Patent Application No. 2006/0031726 entitled “Programmable multi-mode Built-In Self-Test and Self-Repair structure for embedded memory arrays” filed by Zappa et al and published Feb. 9, 2006, a non-volatile (flash) memory and BIST circuitry are shared among several memories. Repair solutions for each memory are stored in a redundancy register of the BISR architecture without immediately storing them in a non-volatile memory array of the device until substitution of all of the faulty addresses by the use of the designated redundancy structures has been verified in order to save test time. Nevertheless, Zappa et al do not disclose a fuse data compression scheme and the disclosed system remains specific to the number, size and configuration of the embedded memory locations and incapable of supporting memories incorporating a mixture of parallel and serial repair approaches and provides no relief to an off-chip tester from information overload during a testing phase.
Accordingly, it is desirable to provide a novel and improved memory repair system that is centralized for an integrated circuit that is independent of the particular number, size and configuration of the embedded memories thereon and accommodates both parallel and serial repair approaches and use of pre-designed circuit blocks.
It is further desirable to provide a novel and improved memory repair system that permits not only download of fuse data from the central fuse box to the various memories during the start-up phase of the integrated circuit, but also facilitates the upload of fuse data into the fuse box and its verification during a testing phase of the manufacture of the integrated circuit.
It is still further desirable to provide a novel and improved memory repair system that reduces the amount of information presented to an off-chip tester during a testing phase and minimizes the amount of resources used to provide this capability.